Debug Control And Status Registers - STMicroelectronics SPC572L series Reference Manual

RM0400
B0
0 1 2 3 4 5 6
B4
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SPR 601 (DVC1U), 318 (DVC1), 602 (DVC2U) 319 (DVC2); Read/Write; Reset: Unaffected
57.3.2

Debug Control and Status registers

Debug Control Registers (DBCR0–8 and EDBRAC0) are used to enable debug events,
reset the processor, and set the debug mode of the processor. The Debug Status register
(DBSR) records debug exceptions while Internal Debug mode is enabled. The Debug Data
Effective Address register (DDEAR) records the effective address of a Data Address
Compare event while Internal Debug mode is enabled.
e200z215An3 requires that a context synchronizing instruction follow a
DBSR to ensure that any alterations enabling/disabling debug events are effective. The
context synchronizing instruction may or may not be affected by the alteration. Typically, an
se_isync instruction is used to create a synchronization boundary beyond which it can be
guaranteed that the newly written control values are in effect.
For watchpoint generation, configuration settings contained in DBCR1–8 are used, even
though the corresponding event(s) may be disabled (via DBCR0) from setting DBSR flags.
57.3.2.1 Debug Control Register 0 (DBCR0)
Debug Control Register 0 is used to enable debug modes and controls which debug events
are allowed to set DBSR or EDBSR0 flags. e200z215An3 adds some implementation
specific bits to this register, as seen in
0 1 2 3 4 5 6
1. DBCR0 is affected by j_trst_b or m_por assertion, and remains reset while in the Test_Logic_Reset state, but is not
EDM
affected by p_reset_b. All other bits are reset by processor reset p_reset_b if DBCR0
m_por. If DBCR0 =1, EDBRAC0 masks off hardware-owned resources (other than RST) from reset by p_reset_b, and
EDM
only software-owned resources indicated by EDBRAC0 and the DBCR0
DBCR0 field will always be reset by p_reset_b regardless of the value of DBCR0
RST
Table 939
B1
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
B5
Figure 987. DVC1, DVC2 registers
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 308; Read/Write; Reset
Figure 988. Debug Control Register 0 (DBCR0) register
provides bit definitions for Debug Control Register 0.
DocID027809 Rev 4
e200z215An3 Core Debug Support
B2
B6
Figure 988.
(1)
- 0x0
EDM
field will be reset by p_reset_b. The
RST
EDM
B3
B7
mtspr
DBCR0–8 or
0 0
=0, as well as unconditionally by
.
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