Table 57. Protected Siul2 Registers - STMicroelectronics SPC572L series Reference Manual

Device configuration
Table 56. Reference links to related information(Continued)
Topic
CMU registers
PMC Digital Interface
(PMC_DIG) registers
PLL Digital Interface
(PLL_DIG) registers
Oscillator Digital Interface
(OSC_DIG) registers
Mode Entry (MC_ME)
registers
Clock Generation Module
(ME_CGM) registers
Reset Generation Module
(MC_RGM) registers
System Status and Control
Module (SSCM) registers
JTAG Master (JTAGM)
registers
6.7.12.1 SIUL2 protected registers
Table 57
Register
SIUL2_DIRER0
SIUL2_DIRSR0
SIUL2_IREER0
SIUL2_IFEER0
MCSR 0–15
MCSR 24–27
MSCR 32–47
MCSR 49
MCSR 51–54
MCSR 56–76
MCSR 109
MCSR 512–527
MCSR 582-583
MCSR 608
174/2058
Related module
CMU, CMUIOP
PMC_DIG
PLLDIG
XOSC
MC_ME
MC_CGM
MC_RGM
SSCM
JTAGM
lists the SIUL2 registers that can be protected.

Table 57. Protected SIUL2 registers

Register size (bits)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
DocID027809 Rev 4
Reference
Chapter 23: Clock Monitor Unit (CMU)
Chapter 54: Power Management Controller digital
interface (PMC_dig)
Chapter 22: PLL Digital Interface (PLLDIG)
Chapter 25: OSC Digital Interface (XOSC)
Chapter 56: Mode Entry Module (MC_ME)
Chapter 24: Clock Generation Module (MC_CGM)
Chapter 51: Reset Generation Module (MC_RGM)
Chapter 53: System Status and Configuration Module
(SSCM)
Offset from module
base address
0x0018
0x0020
0x0028
0x0030
0x0240
(1)
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
RM0400
Protected size (bits)
32
32
32
32
32 (×16)
32 (×4)
32 (×16)
32
32 (×4)
32 (×21)
32
32 (×8)
32 (×2)
32