Figure 1068.L1Sel4 Register Format - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset 0x05
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0
MUX 39
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
63.5.1.1.6 Level1 Mux Selection 5 (L1SEL5)
Figure 1069
L1SEL5 register are device dependent. For a description of these fields, see the device-
specific chapter that describes how the modules are configured.
Offset 0x06
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0
MUX 47
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
63.5.1.1.7 Level1 Mux Selection 6 (L1SEL6)
Figure 1070
L1SEL6 register are device dependent. For a description of these fields, see the device-
specific chapter that describes how the modules are configured.
Offset 0x07
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0
MUX 55
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
63.5.1.1.8 Level1 Mux Selection 7 (L1SEL7)
Figure 1071
L1SEL7 register are device dependent. For a description of these fields, see the device-
specific chapter that describes how the modules are configured. All eight inputs of MUX 63
are tied to logic high (1'b1) and output is always high.
0 0
MUX 38 MUX 37
Figure 1068. L1SEL4 register format
shows the format of the L1SEL5 register. The values for the fields of the
0 0
MUX 46 MUX 45
Figure 1069. L1SEL5 register format
shows the format of the L1SEL6 register.The values for the fields of the
0 0
MUX 54 MUX 53
Figure 1070. L1SEL6 register format
shows the format of the L1SEL7 register. The values for the fields of the
DocID027809 Rev 4
Sequence Processing Unit (SPU)
0 0
MUX 36 MUX 35
0 0
MUX 44 MUX 43
0 0
MUX 52 MUX 51
Access: User read/write
8 7 6 5 4 3
0 0
MUX 34 MUX 33
Access: User read/write
8 7 6 5 4 3
0 0
MUX 42 MUX 41
Access: User read/write
8 7 6 5 4 3
0 0
MUX 50 MUX 49
2 1 0
MUX 32
2 1 0
MUX 40
2 1 0
MUX 48
1827/2058
1863