Path From Mc_Rgm Idle To Serial Boot Mode - STMicroelectronics SPC572L series Reference Manual

Reset and Boot
7.4.4

Path from MC_RGM IDLE to serial boot mode

Here no application program or valid boot header is programmed into flash memory. It is an
unusual scenario, but it is shown here for illustrative purposes.
7.4.4.1 Initial conditions
•
No valid boot header has been programmed into flash memory.
•
BAF bypass mode is NOT enabled (execute BAF code).
•
Application code for the core is programmed into the BAF.
•
Application code for the Boot CPU is not programmed into flash memory.
•
The Life Cycle variable is set to FACTORY, indicating an unprogrammed device.
•
The MC_RGM has passed control to the SSCM during the IDLE state.
7.4.4.2 Reset Generation Module has entered idle state (state 1 and 2)
Once the IDLE phase is signaled, the System Status and Control Module (started in
PHASE3) continues with the system boot-up sequence while the MC_RGM waits for new
events that trigger a reset sequence.
At this point:
•
The data in the DCF record has been written to the appropriate registers.
•
All the trim values for the analog portions of the chip have been installed in their proper
locations.
7.4.4.3 Is a JTAG request pending? (state A)
The SSCM now controls the boot-up sequence and begins by determining if a JTAG request
is pending. The JTAG test circuitry is for production test and use by software development
systems. The JTAG mode has no user functions and should never be used in a user
application. System designers must ensure that the external JTAG request pins cannot
inadvertently cause a JTAG test request.
7.4.4.4 Is the Boot Assist Flash bypass mode enabled? (state B)
The SSCM examines a status bit to determine whether the BAF bypass mode is enabled. If
enabled, any code in the BAF is not executed. The BAF bypass mode is enabled/disabled
using a DCF record.
The DCF record supplied by the factory disables the bypass mode. This means that the
code in the BAF is always executed during a boot-up sequence.
The BAF code written by the device manufacturer also runs the serial boot loader. This
involves setting up pins on the device to act as a UART: receiving a file using a defined
format and transferring the program portion of the file to RAM. Once the program is
installed, the SSCM begins the core execution at the start address specified in the header
portion of the program file.
7.4.4.5 Provide reset vector to Core (state 21)
During PHASE3 of the Reset Generation Module's sequence, the start address for
execution of the BAF code in the Boot Assist Flash is transferred from the DCF record to the
MC_ME by the SSCM.
196/2058 DocID027809 Rev 4
RM0400