External Interrupts/Dma Requests (Eirq Pins) - STMicroelectronics SPC572L series Reference Manual

System Integration Unit Lite2 (SIUL2)
13.3.4

External interrupts/DMA requests (EIRQ pins)

The SIUL2 supports three external interrupts which can be allocated to any pad necessary
at the MCU level. This allocation is fixed per MCU.
The SIUL2 supports two interrupt vectors to the interrupt controller of the MCU. Each
interrupt vector can support three external interrupt sources from the device pads.
Refer to
Interrupt
Vectors
Interrupt
Controller
Glitch filter Prescaler
IFCP[3:0]
Glitch filter Counter_n
MAXCNT[x]
SIUL2_IFER0
All the external interrupt pads within a single group (max 8 pads) have equal priority. It is the
responsibility of the user software to search through the group of sources in the most
appropriate way for their application.
The priority of the vectors used by the external interrupt pads is fixed based on the platform
and the interrupt controller and its priority levels, but the allocation of pads to each group of
interrupts can be independently configured by the MCU.
An MCU-specific number of external interrupt lines can have digital glitch filters applied to
them. The supported range is 1 to 8. The glitch filters need a running internal oscillator clock
to work. If no such clock is available, external interrupts will be effectively disabled when the
glitch filter is enabled on an interrupt line.
306/2058
Figure 73 for an overview of the external interrupt implementation.
Figure 73. External interrupt pad diagram
SIUL2 IRQ 1
EIF[10]
SIUL2 IRQ 0
OR
Interrupt enable
EIF[5], EIF[0]
Edge Detection
Glitch Filter
DocID027809 Rev 4
RM0400
SIUL2_DIRER0
Interrupt Edge Enable
Rising
SIUL2_IREER0
Falling
SIUL2_IFEER0