Fifo Acknowledge Handling - STMicroelectronics SPC572L series Reference Manual

CAN Subsystem
Tx prioritization:
•
Scan all Tx Buffers with activated transmission request
•
Tx Buffer with lowest Message ID gets highest priority and is transmitted next
44.3.13.6 Transmit cancellation
The M_CAN supports transmit cancellation. This feature is especially intended for gateway
applications and AUTOSAR based applications. To cancel a requested transmission from a
dedicated Tx Buffer or a Tx Queue Buffer the Host has to write a '1' to the corresponding bit
position (=number of Tx Buffer) of register TXBCR. Transmit cancellation is not intended for
Tx FIFO operation.
Successful cancellation is signaled by setting the corresponding bit of register TXBCF to '1'.
In case a transmit cancellation is requested while a transmission from a Tx Buffer is already
ongoing, the corresponding TXBRP bit remains set as long as the transmission is in
progress. If the transmission was successful, the corresponding TXBTO and TXBCF bits
are set. If the transmission was not successful, it is not repeated and only the corresponding
TXBCF bit is set.
Note: In case a pending transmission is cancelled immediately before this transmission could
have been started, there follows a short time window where no transmission is started even
if another message is also pending in this node. This may enable another node to transmit a
message which may have a lower priority than the second message in this node.
44.3.13.7 Tx Event handling
To support Tx event handling the M_CAN has implemented a Tx Event FIFO. After the
M_CAN has transmitted a message on the CAN bus, Message ID and timestamp are stored
in a Tx Event FIFO element. To link a Tx event to a Tx Event FIFO element, the Message
Marker from the transmitted Tx Buffer is copied into the Tx Event FIFO element.
The Tx Event FIFO can be configured to a maximum of 32 elements. The Tx Event FIFO
element is described in
full condition is signaled by IR.TEFF, no further elements are written to the Tx Event FIFO
until at least one element has been read out and the Tx Event FIFO Get Index has been
incremented. In case a Tx event occurs while the Tx Event FIFO is full, this event is
discarded and interrupt flag IR.TEFL is set.
To avoid a Tx Event FIFO overflow, the Tx Event FIFO watermark can be used. When the
Tx Event FIFO fill level reaches the Tx Event FIFO watermark configured by
TXEFC[EFWM], interrupt flag IR.TEFW is set.
When reading from the Tx Event FIFO, two times the Tx Event FIFO Get Index
TXEFS[EFGI] has to be added to the Tx Event FIFO start address TXEFC[EFSA].
44.3.14

FIFO acknowledge handling

The Get Indices of Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO are controlled by writing to
the corresponding FIFO Acknowledge Index (see
Acknowledge Register
(RXF1A), and
1072/2058
Section 44.3.6.3: Tx event FIFO
(RXF0A), Section 44.3.5.2.31: Rx FIFO 1 Acknowledge Register
Section 44.3.5.2.43: Tx Event FIFO Acknowledge Register
DocID027809 Rev 4
element. When a Tx Event FIFO
Section 44.3.5.2.27: Rx FIFO 0
RM0400
(TXEFA)). Writing