Peripheral Clock Gating - STMicroelectronics SPC572L series Reference Manual

RM0400
56.4.5.3 SAFE Mode Transition Interrupt
Whenever the system enters the
MC_RGM due to a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register
is set, and an interrupt is generated if the mask bit M_SAFE of ME_IM register is '1' .
The SAFE
deasserted by the MC_RGM (see the MC_RGM chapter for details on how to clear a
mode request). If the system is already in
MC_RGM also sets the interrupt pending bit I_SAFE. However, the
pending bit is not set when the
programming of ME_MCTL register).
56.4.5.4 Mode Transition Complete interrupt
Whenever the system fully completes a mode transition (i.e., the S_MTRANS bit of ME_GS
register transits from '1' to '0'), the interrupt pending bit I_MTC of the ME_IS register is set,
and an interrupt request is generated if the mask bit M_MTC of the ME_IM register is '1'.
The interrupt bit I_MTC is not set when entering low-power modes
order to avoid the same event requesting the immediate exit of these low-power modes.
56.4.6

Peripheral Clock Gating

During all chip modes, each peripheral can be associated with a particular clock gating
policy determined by two groups of peripheral configuration registers.
The run peripheral configuration registers ME_RUN_PC0...7 are chosen only during the
software running modes DRUN, TEST, SAFE, and RUN0...3. All configurations are
programmable by software according to the needs of the application. Each configuration
register contains a mode bit which determines whether or not a peripheral clock is to be
gated. Run configuration selection for each peripheral is done by the RUN_CFG bit field of
the ME_PCTLn registers.
The low-power peripheral configuration registers ME_LP_PC0...7 are chosen only during
the low-power modes
according to the needs of the application. Each configuration register contains a mode bit
which determines whether or not a peripheral clock is to be gated. Low-power configuration
selection for each peripheral is done by the LP_CFG bit field of the ME_PCTLn registers.
Any modifications to the ME_RUN_PC0...7, ME_LP_PC0...7, and ME_PCTLn registers do
not affect the clock gating behavior until a new mode transition request is generated.
Whenever the chip enters a debug session during any mode, the following occurs for each
peripheral:
•
The clock is gated if the DBG_F bit of the associated ME_PCTLn register is set.
Otherwise, the peripheral clock gating status depends on the RUN_CFG and LP_CFG
bits.
56.4.7 Application example
Figure 985
waiting until the mode transition has completed.
mode interrupt pending bit can be cleared only when the
SAFE
HALT0 and STOP0. All configurations are programmable by software
shows an example application flow for requesting a mode change and then
DocID027809 Rev 4
SAFE mode as a result of a
SAFE mode, any new
mode is entered by a software request (i.e.,
Mode Entry Module (MC_ME)
SAFE mode request from the
SAFE mode request is
SAFE mode request by the
SAFE mode interrupt
HALT0 and STOP0
SAFE
in
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