SENT Receiver (SRX)
event) happened in the recent past. Messages are automatically discarded when an error is
detected.
User software can clear these bit at any time by writing 1 to them. This register can be
updated at any time irrespective of the setting in the
Register (CHNL_EN)
Note:
The value of the CH is device-specific. See the Device Configuration chapter for details.
Address Offset = 0x0064 + n × 0x10
0
R BUS_IDLE
W
w1c
Reset
0
8
R
W
Reset
0
16
R
W
Reset
0
24
R
W
Reset
0
Field
Bus Idle Status. This bit indicates that the sensor interface has been idle for more than the period
defined by the programmed Bus Idle Count value (in
Register (n = 0 to (CH-1))
0
BUS_IDLE
0 – Bus is not idle
1 – Channel has been idle for more than the allowed value
1:3
Reserved. Read returns zero
1390/2058
bit for the corresponding channel.
1
2
0
0
9
10
PP_DIAG_
CAL_LEN_
ERR
ERR
w1c
w1c
0
0
17
18
0
0
25
26
0
0
Figure 796. Channel 'n' Status Register (CHn_STATUS)
Table 808. CHn_STATUS field descriptions
(CHn_CONFIG)). CPU should write 1 to this clear this bit once it is read.
3
4
CAL_RESY
NC
w1c
0
0
11
12
CAL_DIAG
NIB_VAL_E
_ERR
RR
w1c
w1c
0
0
19
20
0
0
27
28
0
0
Description
Section 49.3.2.20: Channel 'n' Configuration
DocID027809 Rev 4
Section 49.3.2.2: Channel Enable
5
6
SMSG_OFL
CAL_20_25
W
w1c
w1c
0
0
13
14
SMSG_CR
FMSG_CR
C_ERR
C_ERR
w1c
w1c
0
0
21
22
0
0
29
30
0
0
RM0400
Access: W1C
7
FMSG_OFL
W
w1c
0
15
NUM_EDG
ES_ERR
w1c
0
23
0
31
0
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