STMicroelectronics SPC572L series Reference Manual page 969

RM0400
Offset
ICM Interrupt group register covering DPLL
0x00604
(ICM_IRQG_1)
ICM Interrupt group register covering TIM0,
0x00608
TIM1, TIM2 (ICM_IRQG_2)
0x0060C
ICM Interrupt group register covering MCS0
0x00610
to MCS2 submodules (ICM_IRQG_4)
0x00614
ICM Interrupt group register covering GTM-IP
0x00618 output submodules TOM0 to TOM1
(ICM_IRQG_6)
0x0061C – 0x00620
ICM Interrupt group register covering GTM-IP
0x00624 output submodules ATOM0, ATOM1, ATOM2
and ATOM3 (ICM_IRQG_9)
0x00628 – 0x0062C
ICM Interrupt group register for module error
0x00630
interrupt information (ICM_IRQG_MEI)
ICM Interrupt group register 0 for FIFO
0x00634 channel error interrupt information
(ICM_IRQG_CEI0)
ICM Interrupt group register 1 for TIM0..2
0x00638 channel error interrupt information
(ICM_IRQG_CEI1)
0x0063C
ICM Interrupt group register 3 for MCS0..2
0x00640 channel error interrupt information
(ICM_IRQG_CEI3)
0x00644
0x00648 – 0x007FC
SPE Control status register
0x00800 + AAi
(SPE[i]_CTRL_STAT)
SPE Input pattern definition register
0x00804 + AAi
(SPE[i]_PAT)
0x00808+n*0x04 + SPE Output definition registers
AAi (SPE[i]_OUT_PAT[n]), n = 0...7
SPE output control register
0x00828 + AAi
(SPE[i]_OUT_CTRL)
Table 516. GTMINT module memory map(Continued)
Use
Sensor Pattern Evaluation (SPE) Registers
(AAi = i*0x80, i = 0..1)
DocID027809 Rev 4
GTM101 Integration (GTMINT) Module
Access Reset value
R 0x0000_0000
R 0x0000_0000
Reserved
R 0x0000_0000
Reserved
R 0x0000_0000
Reserved for ICM
R 0x0000_0000
Reserved for ICM
R 0x0000_0000
R 0x0000_0000
R 0x0000_0000
Reserved for ICM
R 0x0000_0000
Reserved for ICM
Reserved
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
(1)
Location
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
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