Table 147. Smpu0_Rgdn_Word1 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
16.4.2.6 Region Descriptor n, Word 1 (SMPU0_RGDn_WORD1)
Address
SMPU0_RGDn_WORD1 – FC01_0404h + (16 × n), where n = 0 to 11
:
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 89. Region Descriptor n, Word 1 (SMPU0_RGDn_WORD1)
Field
End address
0–31
Defines the byte end address of the memory region.
ENDADDR
Note: The SMPU does not verify that ENDADDR ≥ SRTADDR.
16.4.2.7 Region Descriptor n, Word 2 Format 0 (SMPU0_RGD_WORD2_FMT0)
RGD_WORD2 has two formats as determined by the RGD_WORD3[FMT] field.
Note: RGD_WORD2_FMT0 applies when RGD_WORD3[FMT] = 0.
RGD_WORD2_FMT0 defines the access control rights of the memory region on a per
master basis. The access control rights are defined by separate read and write
permissions. For these fields, the bus master number refers to the logical bus master
number.
For the access control rights, there are two flags per logical bus master:
•
Read (r) permission refers to the ability to access the referenced memory address
using an operand (data) fetch or an instruction fetch.
• Write (w) permission refers to the ability to update the referenced memory address
using a store (data) instruction.
Each field consists of the two flags, with (r) being in the more significant position. For
example, M0P has (r) as bit 0 and (w) as bit 1.
The bit settings are as follows:
•
If set, the corresponding flag allows the specific access type (r = memory read, w =
memory write).
•
If cleared, the specific access type is not allowed.
Writes to this word clear the region descriptor's valid bit.
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0

Table 147. SMPU0_RGDn_WORD1 field descriptions

DocID027809 Rev 4
System Memory Protection Unit (SMPU)
6 7 8 9
ENDADDR
0 0 0 0
22 23 24 25
ENDADDR
0 0 0 0
Description
Access: Supervisor read/write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
14 15
0 0
30 31
0 0
335/2058
344