Table 238. Pcs Divider Start Register 2 (Cgm_Pcs_Divs2) Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address 0x0714
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R
W
Reset 0 0 0
Figure 186. PCS Divider Start Register 2 (CGM_PCS_DIVS2)

Table 238. PCS Divider Start Register 2 (CGM_PCS_DIVS2) field descriptions

Field
0–11 Reserved
12–31 Divider Start Value — This is the start value of the clock divider for the clock ramp-up phase when
switching to the PLL0 PHI.
DIVS
24.3.1.7 PCS Divider End Register 2 (CGM_PCS_DIVE2)
This register defines the final division value for the progressive system clock switching when switching
the system clock source from the PLL0 PHI on ramp-down. See
Clock Switching for details on how to set This value.
Note: Byte and half-word write accesses are not allowed for this register. Such accesses do not
result in an exception, but the value is not loaded with the new value.
Address 0x0718
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R
W
Reset 0 0 0
Figure 187. PCS Divider End Register 2 (CGM_PCS_DIVE2)
Table 239. PCS Divider End Register 2 (CGM_PCS_DIVE2) field descriptions
Field
0–11 Reserved
12–31 Divider End Value — This is the clock divider end value for the clock ramp-down phase when
switching from the PLL0 PHI.
DIVE
3 4 5 6
0 0 0 0
0 0 0 0
19 20 21 22
0 0 0 1
3 4 5 6
0 0 0 0
0 0 0 0
19 20 21 22
0 0 0 1
DocID027809 Rev 4
Clock Generation Module (MC_CGM)
Access: User read/write, Supervisor read/write, Test read
7 8 9 10
0 0 0 0
0 0 0 0
23 24 25 26
DIVS[15:0]
1 1 1 1
Description
Section 24.4.1.2, Progressive System
Access: User read/write, Supervisor read/write, Test read
7 8 9 10
0 0 0 0
0 0 0 0
23 24 25 26
DIVE[15:0]
1 1 1 1
Description
11 12 13 14
0
DIVS[19:16]
0 0 0 0
27 28 29 30
0 0 1 1
11 12 13 14
0
DIVE[19:16]
0 0 0 0
27 28 29 30
0 0 1 1
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15
0
31
1
15
0
31
1
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