Memory Map And Register Definition - STMicroelectronics SPC572L series Reference Manual

Clock Monitor Unit (CMU)
23.4

Memory map and register definition

This section describes in address order all the CMU registers. Each description includes a
standard register diagram with an associated figure number. The CMU memory map is
listed in Table
Offset (hex)
0000 CMU Control Status Register (CMU_CSR)
0004 CMU Frequency Display Register (CMU_FDR)
0008 CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)
000C CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)
0010 CMU Interrupt Status Register (CMU_ISR)
0014 Reserved
0018 CMU Measurement Duration Register (CMU_MDR)
Note: See the "Clocking" chapter for register and field availability details.
23.4.1 Register descriptions
23.4.1.1 CMU Control Status Register (CMU_CSR)
Address: Base + 0000h
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1
Not all CMU blocks utilize this feature. See the "Clocking" chapter for device specific CMU implementation
details.
488/2058
225.
Table 225. CMU memory map
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 174. CMU Control Status Register (CMU_CSR)
Register
6 7 8
0 0 0
0 0 0 0
22 23 24 25
0 0
CKSEL11
0 0 0 0
DocID027809 Rev 4
Access: User read/write
9 10 11 12
0 0 0
0 0 0
26 27 28
0 0 0
0 0 0
RM0400
Location
on page 488
on page 489
on page 490
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on page 492
13 14 15
0 0 0
0 0 0
29 30 31
RCDIV1 CME
0 0 0