Table 582. Calibration Status Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

CAN Subsystem
counted down to zero, the calibration FSM transits back to state Basic_Calibrated
(CSTAT.CALS = "01").
The Calibration Watchdog Counter is clocked by the sample point input (cu_spt). The
duration of a cu_spt pulse is one cu_tqc period. The signal is active when the CAN protocol
engine on the attached M_CAN is started i.e. when the INIT bit is reset.
A calibration watchdog event is signaled by output cu_cwe. The duration of a cu_cwe pulse
is one cu_hclk period.
A calibration watchdog event also sets interrupt flag cuir.cwe. If enabled by cuie.cwee,
interrupt line cu_int is activated (set to high). Interrupt line cu_int remains active until
interrupt flag cuir.cwe is reset.
Address: 0x3
0 1 2
R
W
Reset 0 0 0
16 17 18
R
W
Reset 0 0 0
1. Write access by the Host CPU to registers/bits marked with "P=Protected Write" is possible only when input cu_cce = '1'.
Signal cu_cce is activated when the M_CAN control bits CCCR.CCE = '1' AND CCCR.INIT = '1'.
Field
Calibration State
00 Not_Calibrated
0:15
01 Basic_Calibrated
WDV]
10 Precision_Calibrated
11 reserved
16:31
Reserved
WDC
44.3.16.3.6 CU Interrupt Register (CUIR)
The flags are set when one of the listed conditions is detected (edge-sensitive). The flags
remain set until the Host clears them. A flag is cleared by writing a '1' to the corresponding
bit position. Writing a '0' has no effect. A hard reset will clear the register. The configuration
of CUIE controls whether an interrupt is generated.
1080/2058
3 4 5
0 0 0
19 20 21
0 0 0
Figure 535. Calibration Watchdog (CWD)

Table 582. Calibration Status Register field descriptions

DocID027809 Rev 4
6 7 8 9
WDV
0 0 0 0
22 23 24 25
(1)
WDC
0 0 0 0
Description
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
RM0400
Access: RP
14 15
0 0
30 31
0 0