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RM0400
Offset 0x100 + (0x100*n) + 0x00
31
30
29
R
W
Reset
0
0
15
14
13
R
0
0
W
Reset
0
0
Figure 300. Error Injection Channel n Descriptor, Word0 (EICHDn.Word0)
Table 336. Error Injection Channel n Descriptor, Word0 (EICHDn.Word0) field description
Name
31-24
CHKBIT_MASK
33.2.2.3.2 Error Injection Channel n Descriptor, Word1 (EICHDn.Word1)
The second word of the Error Injection Channel n Descriptor defines the 32-bit mask
(UDATA_MASK). Each bit of UDATA_MASK specifies if the corresponding bit of the upper
word on the 64-bit read data bus from the target RAM should be inverted or left unmodified
on read accesses. The upper word corresponds to bits 63–32 of the 64-bit read data bus.
Successful writes to this word clear the corresponding error injection channel valid bit,
EICHEN[EICHnEN].
Offset 0x100 + (0x100*n) + 0x04
31
30
29
R
W
Reset
0
0
15
14
13
R
W
Reset
0
0
Figure 301. Error Injection Channel n Descriptor, Word1 (EICHDn.Word1)
28
27
26
CHKBIT_MASK
0
0
0
0
12
11
10
0
0
0
0
0
0
0
0
Checkbit Mask.
This field defines a bit-mapped mask that specifies if the corresponding bit of the checkbit
bus from the target RAM should be inverted or left unmodified.
0 The corresponding bit of the checkbit bus is left unmodified.
1 The corresponding bit of the checkbit bus is inverted.
28
27
26
0
0
0
0
12
11
10
0
0
0
0
DocID027809 Rev 4
25
24
23
22
0
0
0
0
0
0
9
8
7
6
0
0
0
0
0
0
0
0
Description
25
24
23
22
UDATA_MASK
0
0
0
0
9
8
7
6
UDATA_MASK
0
0
0
0
Error Injection Module (EIM)
Access: Supervisor
21
20
19
18
0
0
0
0
0
0
0
0
5
4
3
2
0
0
0
0
0
0
0
0
Access: Supervisor
21
20
19
18
0
0
0
0
5
4
3
2
0
0
0
0
Read/Write
17
16
0
0
0
0
1
0
0
0
0
0
Read/Write
17
16
0
0
1
0
0
0
689/2058
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