Figure 345. Watchdog Threshold Registers 4–15 (Wthrhlr4–Wthrhlr15) - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
Field
Conversion result mode status
This bit reflects the mode of conversion for the corresponding channel.
14–15
00 Data is a result of Normal conversion mode
RESULT[1:0]
01 Data is a result of Injected conversion mode
10 Data is a result of CTU conversion mode
11 Reserved
Channel converted data
Note: If MCR[WLSIDE] is set to '0' than the converted data is read right aligned with lower 12/10
bits representing the actual converted data(width of actual converted data depends on selected
resolution of current conversion, selectable by CTRx[CRES] bit) and remaining upper 4/6 bits
16–31
are read as zeros.
CDATA
Whereas if the MCR[WLSIDE] is set as '1' than the converted data is read left aligned with upper
12/10 bits representing the actual converted data(width of actual converted data depends on
selected resolution of current conversion, selectable by CTRx[CRES] bit) and remaining lower
4/6 bits are read as zeros.
The length of the useful converted data out of 16 bits of CDATA field also depends on the
generic resolution and conv_mode_select.
As each of ICDRx corresponds to an internal channel inferred through generic num_intch. If
any of the num_intch(i) values is '0', the corresponding ICDRx is not implemented and any
attempt to access this space generates a transfer error.
This register should be accessed via 32-bit R/W.
The REFSEL bit implementation is dependent on parameter vector altref_exists_ch[95:0].
36.5.1.17 Watchdog Threshold Registers 4–15 (WTHRHLR4–WTHRHLR15)
Offset 0x280–0x2AC
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Figure 345. Watchdog Threshold Registers 4–15 (WTHRHLR4–WTHRHLR15)
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Table 390. ICDR0–ICDR95 field descriptions(Continued)
2 3 4 5
0 0
0 0 1 1
18 19 20 21
0 0
0 0 0 0
DocID027809 Rev 4
Description
6 7 8 9
THRH
1 1 1 1
22 23 24 25
THRL
0 0 0 0
Access: User Read/Write
10 11 12 13
1 1 1 1
26 27 28 29
0 0 0 0
14 15
1 1
30 31
0 0