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Mode Entry Module (MC_ME)
56.3.2.8
RESET
Address 0x020
0
1
2
R
0
PWRLVL
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
Figure 965. RESET Mode Configuration Register (ME_RESET_MC)
This register configures system behavior during
details.
Note:
The following configuration values are set according to the chip configuration: XOSCON
56.3.2.9
TEST
Mode Configuration Register (ME_TEST_MC)
Address 0x024
0
1
2
R
0
PWRLVL
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
Figure 966. TEST Mode Configuration Register (ME_TEST_MC)
This register configures system behavior during
details.
Note:
Byte write accesses are not allowed to this register.
1616/2058
Mode Configuration Register (ME_RESET_MC)
3
4
5
0
0
0
0
0
19
20
21
0
0
0
0
0
0
3
4
5
0
0
0
0
0
19
20
21
0
0
0
0
0
0
DocID027809 Rev 4
Access: User read, Supervisor read/write, Test read/write
6
7
8
9
0
0
PDO
0
0
0
0
0
22
23
24
25
0
0
0
0
0
0
0
RESET
Access: User read, Supervisor read/write, Test read/write
6
7
8
9
0
0
0
PDO
0
0
0
0
22
23
24
25
0
0
0
0
0
0
0
TEST
10
11
12
13
0
0
0
0
1
0
0
26
27
28
29
SYSCLK
0
1
0
0
mode. Please refer to
10
11
12
13
0
0
0
0
1
0
0
26
27
28
29
SYSCLK
0
1
0
0
mode. Please refer to
RM0400
14
15
FLAON
1
1
30
31
0
0
Table 928
for
14
15
FLAON
1
1
30
31
0
0
Table 928
for
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