STMicroelectronics SPC572L series Reference Manual page 974

GTM101 Integration (GTMINT) Module
Offset
(0x0D030 –
0x0D03C) +
m*0x0080 + DDi
AGC Global control register
0x0D040 + DDi
(ATOM[i]_AGC_GLB_CTRL)
AGC0 Enable/disable control register
0x0D044 + DDi
(ATOM[i]_AGC_ENDIS_CTRL)
AGC Enable/disable status register
0x0D048 + DDi
(ATOM[i]_AGC_ENDIS_STAT)
AGC Action time base register
0x0D04C + DDi
(ATOM[i]_AGC_ACT_TB)
AGC Output enable control register
0x0D050 + DDi
(ATOM[i]_AGC_OUTEN_CTRL)
AGC Output enable status register
0x0D054 + DDi
(ATOM[i]_AGC_OUTEN_STAT)
AGC Force update control register
0x0D058 + DDi
(ATOM[i]_AGC_FUPD_CTRL)
AGC Internal trigger control register
0x0D05C + DDi
(ATOM[i]_AGC_INT_TRIG)
(0x0D040 –
0x0D05C) +
m*0x0080 + DDi
(0x0D060 –
0x0D07C) +
m*0x0080 + DDi
(0x0D400 –
0x0D7FC) + DDi
0x0E800 – 0x12C40
0x12C44 – 0x17FFC
F2A read channel address register
0x18000+m*0x04
(F2A[i]_CH[m]_ARU_RD_FIFO)
F2A stream x configuration register
0x18020+m*0x04
(F2A[i]_CH[m]_STR_CFG)
F2A stream activation register
0x18040
(F2A[i]_ENABLE)
0x18044 – 0x1807C
AFD FIFO m buffer access register
0x18080+m*0x10
(AFD[i]_CH[m]_BUFF_ACC)
974/2058
Table 516. GTMINT module memory map(Continued)
Use
F2A Configuration Registers (m = 0...7, i = 0, EEi = 0x4000)
AFD Registers (m = 0...7, i = 0, EEi = 0x4000)
DocID027809 Rev 4
Access
Reserved for ATOM[i]_CH[m]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved for ATOM[i]_CH[m], m>1
Reserved for ATOM[i]_CH[m]
Reserved for ATOM[i]
Reserved for ATOM3 to ATOM11
Reserved
R/W
R/W
R/W
Reserved
R/W
(1)
Reset value Location
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_01FE See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
RM0400
2
2
2
2
2
2
2
2
2
2
2
2