Software Interface - STMicroelectronics SPC572L series Reference Manual

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62.2.6

Software interface

It is possible for software to write the 120 bits of JTAG data to be output and to read the 60
bits of data. The JTAGM module has an IPS interface.
62.3 Modes of operation
There are no special modes of operation. The JTAGM works normally in the debug mode.
62.4 Memory map and register definition
Table 1006
Offset
0x00 Module Configuration Register (JTAGM_MCR)
0x04 Status Register (JTAGM_SR)
0x08 Data Out Register 0 (JTAGM_DOR0)
0x0C Data Out Register 1 (JTAGM_DOR1)
0x10 Data Out Register 2 (JTAGM_DOR2)
0x14 Data Out Register 3 (JTAGM_DOR3)
0x18 Reserved
0x1C Data Input Register 0 (JTAGM_DIR0)
0x20 Data Input Register 1 (JTAGM_DIR1)
62.4.1 Register descriptions
62.4.1.1 Module configuration register (JTAGM_MCR)
Figure 1054
contains the memory map of the JTAGM registers.
Table 1006. Memory map
shows the format of the JTAGM_MCR.
DocID027809 Rev 4
Register
JTAG Master (JTAGM)
Location
on page 1807
on page 1809
on page 1811
on page 1812
on page 1812
on page 1812
on page 1813
on page 1813
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1814