Loss Of Lock - STMicroelectronics SPC572L series Reference Manual

RM0400
22.6.3

Loss of lock

The PLL digital interface registers provide the flexibility to select whether to generate an
interrupt assert system reset or do nothing in the event that the PLL loses lock according to
the available PLLnCR options.
Loss of lock reset and interrupt are only generated when the PLL is operating in normal
mode.
The lock indication from the analog PLL is synchronized and stored in the status register.
When the analog PLL loses lock or regains lock, it will be immediately indicated in the status
register (after synchronization time).
A pair of counters monitor the reference and feedback clocks to determine when the system
has acquired frequency lock. Once the PLL has locked, the counters continue to monitor the
reference and feedback clocks and report whether the PLL has lost lock. The lock status is
indicated in the status register.
1. Power down by writing MC_ME_<mode>_MC[PLL0ON] = 0, followed by a mode
change
2. Write a mode change to MC_ME_<mode>_MC[PLL0ON].
3. Power up the PLL by writing MC_ME_<mode>_MC[PLL0ON] = 1, followed by a mode
change.
4. Write a mode change to MC_ME_<mode>_MC[PLL0ON].
22.7 Initialization information
Coming out of reset the PLL is disabled per the DRUN mode configuration register,
MC_ME_DRUN_MC. The PLLDIG initialization porcedure is described in the "Clocking"
chapter.
DocID027809 Rev 4
PLL Digital Interface (PLLDIG)
485/2058
485