Features - STMicroelectronics SPC572L series Reference Manual

Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface
35.3

Features

• 16-bit data resolution output
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Single-ended input or differential input mode of operation
• Programmable wraparound mechanism for both modes of operation
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Configurable biasing for negative input terminal in single-ended mode
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Gain and offset calibration support using fixed bias for input terminals
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Programmable decimation rate
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Programmable gain for analog inputs
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Optional external modulator support
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Optional high-pass filter for pure AC application
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Hardware trigger support for synchronous operation of multiple SDADC blocks
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Trigger event output generation by software
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Programmable FIFO structure for storing 16-bit converted data
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Interrupt/DMA request generation based on various conditions:
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Low consumption mode
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Optional conversion process halt mechanism on SoC debug request
35.4 Modes of operation
This section describes the different operation modes of the SDADC. When exiting reset, the
mode of operation is determined by the Module Configuration Register (MCR).
35.4.1 Differential input mode
This mode is entered by negating the MCR[MODE] bit. In this mode, a pair of analog inputs
are connected to positive and negative terminals of ADC modulator. In order to support gain
and offset calibration for diagnostics, it is possible in this mode to select fixed bias voltages
to both input terminals.
35.4.2 Single-ended input mode
This mode is entered by asserting the MCR[MODE] bit. In this mode, the negative input
terminal is biased with a fixed voltage based on selection information in MCR, and the other
analog input is connected to the selected external analog channel.
35.4.3 External modulator mode
This mode is entered by asserting the MCR[EMSEL] bit. In this mode, the data stream and
clock outputs from the external modulator available on EMDATA/EMCLK input pins are
routed directly to the SDADC block. The internal modulator is bypassed in this mode. Only
the digital filters of the SDADC will be used for result calculation. The source for the external
modulator clock can be the internal on-chip clock source or the direct clock output coming
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Configurable trigger sources: hardware or software
Configurable initial entry and wraparound values for the loop
Data buffer at or above threshold
Data buffer overrun
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