Dsmc Instantiations - STMicroelectronics SPC572L series Reference Manual

Decorated Storage Memory Controller (DSMC)
30.5

DSMC Instantiations

The decorated storage memory controller which performs these operations is instantiated
multiple times within the core platform and physically resides between the slave ports of the
crossbar and the targeted memory controllers.
The module includes error checking logic that validates the decoration field is properly
defined (all illegal commands are rejected and the transfer error terminated). Additionally,
the decorated memory controller only operates on aligned, single data transfers
(misalignment and/or bursts are not supported and error terminated if attempted).
As the DSMC generates the atomic read-modify-write bus transactions to the attached slave
memory controller, the two transactions (read, write) are fully pipelined with no idle cycles
introduced. During these transactions, the AHB hlock control signal is asserted to the slave
during the entire read-modify-write.
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Figure 284. DSMC Timing Diagram
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