Table 23. Latency Time Categories - STMicroelectronics SPC572L series Reference Manual

RM0400
IRQ # Offset
931 GTM_ERR_IRQ
Decimation filter input buffer interrupt request
932 1E90
flag
Decimation filter output buffer interrupt request
933 1E94
flag
934 1E98 Decimation filter error interrupt request flag
935 1E9C Clock Calibration on CAN event
6.3.6.3 Interrupt latency
The interrupt system is designed to provide a very short latency between the assertion of an
interrupt request from a peripheral and the first instruction of the Interrupt Service Routine.
The latency time is difficult to define exactly because it depends on what interrupts the INTC
is processing and what the CPU is doing.
The latency time is divided into 3 general categories, as per the following table:
Category
INTC latency
CPU latency
Software latency
INTC operates at 40 MHz and the CPU operates at 80 MHz for SPC572Lx, so the interrupt
latency is:
• INTC latency = 75 ns
•
CPU latency = 50 ns
• Software latency = 87.5 ns
•
Interrupt latency total = 212.5 ns
Table 22. Interrupt sources(Continued)
Source description

Table 23. Latency time categories

3 clock cycles (INTC clock domain) from the assertion of the interrupt
request from the peripheral to assertion of the interrupt request to the
CPU
4 clock cycles (CPU clock domain) from the assertion of the interrupt
request from the INTC to the execution of the first instruction
7 clock cycles (CPU clock domain) to execute the 3 instructions needed to
save essential registers and enable interrupts
DocID027809 Rev 4
Source name
gtm_err_irq
DECI_FILTR[IBIF]
DECI_FILTR[OBIF]
DECI_FILTR[DIVR] DECI_FILTR[OVF]
DECI_FILTR[OVR] DECI_FILTR[IVR]
DECI_FILTR[SVR] DECI_FILTR[SCE]
DECI_FILTR[SSE]
cu_int
Details
Device configuration
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