Table 938. Dac Events And Resultant Updates - STMicroelectronics SPC572L series Reference Manual

RM0400
following completion of the access, if the first load or store class instruction generates a
DVC DAC, a second and possibly third load or store class instruction may also generate a
DAC or DVC DAC event, or may generate a DSI exception with or without a simultaneous
DAC event.
Also, since non-load/store instructions may be dual-issued in combination with a load/store
instruction, the actual number of additional instructions that are completed following a
recognized DVC DAC on a load/store instruction may vary from 0 to 5. This value will be
reported in the DBSR
Table 938
the ESR register for various exception cases on sequences of load/store class instructions.
Not all exception combinations are covered in the table, such as IAC, ISI, or Alignment
exceptions on subsequent instructions. In general these exceptions will cause further
instruction issue to be halted, execution of the excepting instruction to be aborted, and
reporting of these exceptions will be masked. The saved DSRR0 value will point to this
excepting instruction, and the exception(s) may be regenerated after returning from the
debug interrupt handler and attempting to re-execute the instruction pointed to by DSRR0.
2nd
instruction
1st
load/store
(load/store
class
class unless
instruction
otherwise
specified)
DSI, no DAC —
DSI, with
—
DACx
DACx —
No
exceptions,
DVC DACx
any
instruction
No
DVC DACx
exceptions
DVC DACx DSI, no DAC
DSI, with
DVC DACx
DACy
field when the DVC DAC status is recorded.
DAC_OFST
outlines the settings of the DBSR, DSRR0 saved value, and potential updating of

Table 938. DAC events and resultant updates

3rd
instruction
(load/store
class unless
otherwise
specified)
— Take DSI exception, no DBSR update. Update ESR.
Take Debug exception, DBSR update setting DACx and IDE,
— DAC_OFST not set. DSRR0 points to 1st load/store class
instruction. No ESR update.
Take Debug exception, DBSR update setting DACx, DAC_OFST
— not set. DSRR0 points to 2nd load/store class instruction. No ESR
update.
No
exceptions, Take Debug exception, DBSR update setting DACx, DAC_OFST set
Non-ldst to 3'b001. DSRR0 points to 3rd instruction. No ESR update.
instruction
No
Take Debug exception, DBSR update setting DACx, DAC_OFST set
exceptions,
to 3'b010. DSRR0 points to instruction after 3rd instruction. No ESR
Ldst
update.
instruction
Take Debug exception, DBSR update setting DACx, DAC_OFST
not set. DSRR0 points to 2nd load/store class instruction. No ESR
update.
—
Note: in this case the 2nd ld/st exception is masked. This behavior is
Take Debug exception, DBSR update setting DACx. DAC_OFST
not set. DSRR0 points to 2nd load/store class instruction. No ESR
update.
—
Note: in this case the 2nd ld/st exception is masked. This behavior is
DocID027809 Rev 4
e200z215An3 Core Debug Support
implementation dependent and may differ on other CPUs.
implementation dependent and may differ on other CPUs.
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