Overriding Secure Read Protection - STMicroelectronics SPC572L series Reference Manual

RM0400
Referring to
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For LOCK3_PG0
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For LOCK3_PG1
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• For LOCK3_PG2
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• For LOCK3_PG3
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31.4.2

Overriding secure read protection

As noted previously, the PASS_LOCK3_PGn registers (see
protection fields, RP0–RP4, that correspond to pre-defined Read Lock groups. To
temporarily unlock a Read Lock group, the appropriate PASS_LOCK3_PGn[RLn] bits must
be set to 0.
Like the register bits controlling secure write protection, the reset value of bits controlling
secure read protection is determined by DCF record or, in the absence of a relevant DCF
record, each bit resets to '1', causing the blocks associated with each read group to be read
locked.
Building on
temporarily overriding secure read protection for that group is accomplished by first
unlocking the PASS_LOCK3_PG0 and PASS_LOCK3_PG1 registers and then setting the
RL3 bit to '0' in both.
Figure 289, the values for the DCF record are:
Data[31:0] is 0x0008_0000 (bits 0–31)
CS[14:0] is 0b000_0000_0000_1000 (bits 32–46)
Address[16:2] is 0b000_0000_0100_0011 (bits 47–61)
Parity value is irrelevant because it is not used in PASS DCF records (bit 62)
Preferred Stop value is 0.
Data[31:0] is 0x0008_0000 (bits 0–31)
CS[14:0] is 0b000_0000_0000_1000 (bits 32–46)
Address[16:2] is 0b000_0000_0100_0111 (bits 47–61)
Parity value is irrelevant because it is not used in PASS DCF records (bit 62)
Preferred Stop value is 0.
Data[31:0] is 0x0000_0000 (bits 0–31)
CS[14:0] is 0b000_0000_0000_1000 (bits 32–46)
Address[16:2] is 0b000_0000_0100_1011 (bits 47–61)
Parity value is irrelevant because it is not used in PASS DCF records (bit 62)
Preferred Stop value is 0.
Data[31:0] is 0x0000_0000 (bits 0–31)
CS[14:0] is 0b000_0000_0000_1000 (bits 32–46)
Address[16:2] is 0b000_0000_0100_1111 (bits 47–61)
Parity value is irrelevant because it is not used in PASS DCF records (bit 62)
Preferred Stop value is 0.
Example 17. Overriding secure read protection
Example 16, where Read Lock group 3 was protected by passwords 0 and 1,
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Flash Memory Programming and Configuration
Figure 292) contain five read
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