Table 1084. Ds Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits Name
31 DBG
30:28 LPS
27:26 LPC
25:0 —
66.4.7 Watchpoint Trigger (WT, PTSTC, PTETC, DTSTC, DTETC) registers
The Watchpoint Trigger Registers allows the watchpoints defined within the Nexus1 logic to
trigger actions. These watchpoints can control Program and/or Data Trace enable and
disable. The control bits can be used to produce a related "window" for triggering Trace
Messages. Watchpoint trigger register WT is used to control triggering by a single selected
watchpoint. The Program Trace Start Trigger Control (PTSTC), Program Trace End Trigger
Control (PTETC), Data Trace Start Trigger Control (DTSTC), and Data Trace End Trigger
Control (DTETC) are used for extended trigger controls for the respective function. If
multiple watchpoints are desired for triggering, or a watchpoint beyond watchpoint #13 is
required, then one or more of the extended watchpoint trigger registers may be used. A field
encoding of 4'b1111 in one of the WT register fields enables the corresponding extended
trigger register. For all other WT field encodings, the corresponding extended trigger register
is disabled and the contents are ignored. Note that direct writes to enable program trace
and/or data trace in DC1 will override these controls, and trace will remain enabled until
another direct write to DC1 to disable program and/or data trace occurs.
When a start trigger is detected, the designated trace features become enabled, and the
corresponding enable bits of the DC1 register are set. Whenever a stop trigger is detected,
the designated trace features become disabled, and the corresponding enable bits of the
DC1 register are cleared. If the same trigger condition is used for both start and stop
triggering, then the designated trace features will toggle between being enabled and
disabled at each occurrence of the trigger condition. Similarly, if start and stop triggers for a
trace feature occur simultaneously, then the designated trace feature will toggle between
enabled and disabled depending on the enable state at the time of the trigger events. For
example, if tracing is enabled, and a start and stop trigger occur simultaneously, then tracing
Nexus Reg# 0x4; DCR: 409; Read-only; Reset: 0x0
Figure 1136. Development Status (DS) register

Table 1084. DS field descriptions

CPU Debug Mode Status
0 CPU not in Debug mode
1 CPU in Debug mode (jd_debug_b signal asserted)
System Low Power Mode Status
000 Normal (Run) mode
001 Waiting State (p_waiting signal asserted
010 Halted State (p_halted signal asserted
011 Reserved
1xx Reserved
CPU Low Power Mode Status
00 Normal (Run) mode
01 CPU in Halted state (p_halted signal asserted)
10 CPU in Stopped state (p_stopped signal asserted)
11 CPU in Waiting state (p_waiting signal asserted)
Reserved for future functionality (read as 0)
DocID027809 Rev 4
e200z215An3 Nexus 3 Module
0
9 8 7
Description
6 5 4 3 2 1 0
1929/2058
1982