Sent Receiver (Srx) Configuration - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Parity Error Stop
30
Controls SPI operation when a parity error is detected in a received SPI frame.
PES 0 SPI frame transmission continues.
1 SPI frame transmission stops.
Halt
31
Starts and stops DSPI transfers.
HALT 0 Start transfers.
1 Stop transfers.
6.7.5

SENT Receiver (SRX) configuration

6.7.5.1 SRX channels
SPC572Lx has one instance of SRX (SRX_0) with four channels.
6.7.5.2 SRX registers
Table 48
for this chip.
Offset
0x0000 GBL_CTRL— Global Control Register
0x0004 CHNL_EN—Channel Enable Register
0x0008 GBL_STATUS—Global Status Register
0x000C FMSG_RDY—Fast Message Ready Register
0x0010 SMSG_RDY—Slow Serial Message Ready Register
0x0014 Reserved
0x0018 DATA_CTRL1— Data Control Register 1
0x001C Reserved
0x0020 Reserved
0x0024 Reserved
0x0028 FDMA_CTRL—Fast Message DMA Control Register
0x002C SDMA_CTRL—Slow Serial Message DMA Control Register
0x0030 Reserved
0x0034 FRDY_IE—Fast Message Ready Interrupt Control Register
0x0038 SRDY_IE—Slow Serial Message Ready Interrupt Control Register
0x003C Reserved
0x0040 DMA_FMSG_DATA—DMA Fast Message Read Register
0x0044 DMA_FMSG_CRC—DMA Fast Message CRC Read Register
Table 47. DSPIx_MCR field descriptions(Continued)
lists the address offset and memory map for both SENT receiver (SRX) instances
Table 48. SENT receiver memory map
DocID027809 Rev 4
Description
Register name
Device configuration
SENT 0
X
X
X
X
X
—
X
—
—
—
X
X
—
X
X
—
X
X
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