Physical Address Lower Register (Palr) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Receive frame control pause. This read-only status bit is asserted when a full duplex flow control
RFC_PAUSE pause frame is received and the transmitter pauses for the duration defined in this pause frame.
This bit automatically clears when the pause duration is complete.
Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the
MAC stops transmission of data frames after the current transmission is complete. At this time,
GRA interrupt in the EIR is asserted. With transmission of data frames stopped, MAC transmits a
TFC_PAUSE
MAC Control PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting
data frames. If the transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
the MAC may continue transmitting a MAC Control PAUSE frame.
Full duplex enable. If set, frames transmit independent of carrier sense and collision inputs. This
FDEN
field must be modified only when ECR[ETHER_EN] = 0.
Heartbeat control. If set, the heartbeat check performs following end of transmission and the HB bit
HBC in the status register is set if the collision input does not assert within the heartbeat window. This
field must be modified only when ECR[ETHER_EN] = 0.
Graceful transmit stop. When this bit is set, MAC stops transmission after any frame currently
transmitted is complete and GRA interrupt in the EIR is asserted. If frame transmission is not
currently underway, the GRA interrupt is asserted immediately. After transmission finishes, clear
GTS to restart. The next frame in the transmit FIFO is then transmitted. If an early collision occurs
GTS
during transmission when GTS is set, transmission stops after the collision. The frame is
transmitted again after GTS is cleared. There may be old frames in the transmit FIFO that transmit
when GTS is reasserted. To avoid this situation, program ECR[ETHER_EN] = 0 following the GRA
interrupt.
48.4.11

Physical Address Lower Register (PALR)

PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used in the address
recognition process to compare with the DA (destination address) field of receive frames
with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte
source address field when transmitting PAUSE frames.
This register is not reset and you must initialize it.
Offset: 0E4h
0 1 2 3
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Field
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are
PADDR1
used for exact match and the source address field in PAUSE frames.
Table 709. TCR field descriptions
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 700. Physical Address Lower Register (PALR)
Table 710. PALR field descriptions
DocID027809 Rev 4
Fast Ethernet Controller (FEC)
Description
PADDR1
Description
Access: User read/write
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