Negating An Interrupt Request Outside Of Its Isr - STMicroelectronics SPC572L series Reference Manual

RM0400
inefficiencies with an ISR whose work spans multiple priorities (as described in
Section 18.7.7.1, Scheduling a lower priority portion of an
priority. However, the INTC has a LIFO whose depth is determined by the number of
priorities.
Note: Lowering the PRI value in INTC_CPRn within an ISR to below the ISR's corresponding PRI
value in INTC_PSRn allows more preemptions than the depth of the LIFO can support.
Therefore, through its use of the LIFO the INTC does not support lowering the current
priority within an ISR as a way to avoid preemptive scheduling inefficiencies.
18.7.9

Negating an interrupt request outside of its ISR

18.7.9.1 Negating an interrupt request as a side effect of an ISR
Some peripherals have flag bits which can be cleared as a side effect of servicing a
peripheral interrupt request. For example, reading a specific register can clear the flag bits,
and consequently their corresponding interrupt requests too. This clearing as a side effect of
servicing a peripheral interrupt request can cause the negation of other peripheral interrupt
requests besides the peripheral interrupt request whose ISR presently is executing. This
negating of a peripheral interrupt request outside of its ISR can be a desired effect.
18.7.9.2 Negating multiple interrupt requests in one ISR
An ISR can clear other flag bits besides its own flag bit. One reason that an ISR clears
multiple flag bits is because it serviced those other flag bits, and therefore the ISRs for these
other flag bits do not need to be executed.
18.7.9.3 Proper setting of interrupt request priority
Whether an interrupt request negates outside of its own ISR due to the side effect of an ISR
execution or the intentional clearing of a flag bit, the priorities of the peripheral or software-
settable interrupt requests for these other flag bits must be selected properly. Their PRIn
values in INTC_PSRn must be selected to be at or lower than the priority of the ISR that
cleared their flag bits. Otherwise, those flag bits still can cause the interrupt request to the
processor to assert. Furthermore, the clearing of these other flag bits also has the same
timing relationship to the writing to INTC_SSCIRn as the clearing of the flag bit that caused
the present ISR to be executed. Refer to
handler for more information.
A flag bit whose enable bit or mask bit is negating its peripheral interrupt request can be
cleared at any time, regardless of the peripheral interrupt request's PRIn value in
INTC_PSRn.
18.7.10 Examining LIFO contents
There are multiple methods for tracking interrupts in a system, one of which is described
here using existing hardware (LIFO) within the INTC. Although the LIFO contents are not
memory-mapped, the user can read the contents by popping the LIFO and reading the PRI
field in the INTC current priority register (INTC_CPRn). To avoid a lower-level interrupt
being serviced because the popping of the LIFO updates the INTC_CPRn, the processor
recognition of interrupts should be disabled when examining LIFO contents. The pseudo-
code is as follows:
wrteei 0 # disable processor recognition of external interrupts
Section 18.6.3.1.2, End of interrupt exception
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Interrupt Controller (INTC)
ISR) is to lower the current
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