Table 606. Sipi_Acr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Serial Interprocessor Interface (SIPI)
Field
Reflects the count value of address counter at target node. It should be configured by direct write request
0–29
from the initiator. This register can be read/written by software anytime. At the end of the streaming
ADCNT
operation, SIPI_ACR will point to the next address to be written.
30-31 Reserved
Note: SIPI_ARR, SIPI_ACR and SIPI_MAXCR will be configured by direct write operation through
the initiator.
Note: When a streaming write command is received, the target will start the write operation from
the address present in SIPI_ACR.
Note: After each 32-bit write has completed, SIPI_ACR[ADCNT] is compared against
SIPI_MAXCR[MXCNT]. If they are equal, SIPI_ACR[ADCNT] is loaded with the value
stored in SIPI_ARR[ADRLD]. If they are not equal, the SIPI_ACR[ADCNT] will increment by
4, decrement by 4, or remain the same (depending on configuration). In either case, the
SIPI_ACR[ADCNT] will contain the address at which the next streaming write will occur.
45.15.1.13 SIPI Channel Error Register (SIPI_ERR)
This register contains the error bits for the last transaction(s) for all the channels.
Communication errors are generated only for out of range address accesses, areas that are
read only and where accesses do not lead to generation of transfer errors. Also, writing to
read only registers will not generate communication errors.
Offset: 00B0h
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Field
0–4 Reserved
Timeout Error for Channel 3.
5
0 Timeout error has occurred
TOE3
1 Timeout error has not occurred
1132/2058

Table 606. SIPI_ACR field descriptions

2 3 4 5
0 0 0
w1c
0 0 0 0
18 19 20 21
0 0 0
w1c
0 0 0 0
Figure 581. SIPI Channel Error Register (SIPI_ERR)
Table 607. SIPI_ERR field descriptions
DocID027809 Rev 4
Description
6 7 8 9
0 0
w1c w1c
0 0 0 0
22 23 24 25
0 0
w1c w1c
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0
w1c
0 0 0 0
26 27 28 29
0 0 0
w1c
0 0 0 0
RM0400
14 15
w1c w1c
0 0
30 31
w1c w1c
0 0