Table 940. Dbcr1 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
Bit Name
Critical Return Debug Event Enable
26 CRET
0 CRET debug events are disabled
1 CRET debug events are enabled
27:31 — Reserved
57.3.2.2 Debug Control Register 1 (DBCR1)
Debug Control Register 1 is used to configure Instruction Address Compare operation. The
DBCR1 register is shown in
0 1 2 3 4 5 6
1. Reset by processor reset p_reset_b if EDBCR0
EDBRAC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by
EDBRAC0 will be reset by p_reset_b.
Table 940
Bit Name
Instruction Address Compare 1 User/Supervisor Mode
00 IAC1 debug events not affected by MSR
0:1 IAC1US
01 Reserved
10 IAC1 debug events can only occur if MSR
11 IAC1 debug events can only occur if MSR
Instruction Address Compare 1 Effective/Real Mode
00 IAC1 debug events are based on effective address
2:3 IAC1ER
01 Unimplemented (Book E real address compare), no match can occur
10 IAC1 debug events are based on effective address and can only occur if MSR
11 IAC1 debug events are based on effective address and can only occur if MSR
Instruction Address Compare 2 User/Supervisor Mode
00 IAC2 debug events not affected by MSR
4:5 IAC2US
01 Reserved
10 IAC2 debug events can only occur if MSR
11 IAC2 debug events can only occur if MSR
Instruction Address Compare 2 Effective/Real Mode
00 IAC2 debug events are based on effective address
6:7 IAC2ER
01 Unimplemented (Book E real address compare), no match can occur
10 IAC2 debug events are based on effective address and can only occur if MSR
11 IAC2 debug events are based on effective address and can only occur if MSR
1660/2058
Table 939. DBCR0 field descriptions (Continued)
Figure
0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 309; Read/Write; Reset
Figure 989. DBCR1 register
EDM
provides bit definitions for Debug Control Register 1.

Table 940. DBCR1 field descriptions

DocID027809 Rev 4
Description
989.
(1)
- 0x0
=0, as well as unconditionally by m_por. If EDBCR0
Description
PR
=0 (Supervisor mode)
PR
=1. (User mode)
PR
PR
=0 (Supervisor mode)
PR
=1. (User mode)
PR
RM0400
0
=1,
EDM
=0
IS
=1
IS
=0
IS
=1
IS