Receiver Diagnostics - STMicroelectronics SPC572L series Reference Manual

RM0400
in the sensor input signal, the 8-bit counter resets and starts counting up on the high
frequency receiver clock. As long as the new state is stable on the pin, the counter remains
incrementing. If a counter overflows occurs, the new pin value (i.e. sensor input) is validated
and latched in the filtered output flop (also running on high frequency receiver clock). If the
opposite edge appears on the sensor input before validation (i.e. overflow), the counter is
reset and the input is not passed onto the filtered output. At the next pin transition, the
counter starts counting again. Any pulse that is shorter than a full range of the masked
counter is regarded as a glitch and it is not passed on to the filter output. The number of
samples (or the match value of the up counter) is programmable by the user in the channel's
configuration register
1)) (CHn_CONFIG)). When zero is programmed into the registers, it bypasses the filter and
the synchronized input is output as the filtered output. A non-zero value delays the filtered
output by the number of clocks proportional to the programmed value in the Channel
Configuration Register
1)) (CHn_CONFIG)). A timing diagram of the input filter is shown in
High Frequency
Input Clock
ipp_ind_sent_rx
14-bit Prescaler
Counter
Filtered Output
49.4.7

Receiver diagnostics

Most of the receiver diagnostics are controlled by the Fast Message State Machine. The
following checks are conducted by the receiver in each channel
•
Calibration pulse length < 56 clock ticks – 25% or > 56 clock ticks + 25%
• Not the expected number of falling edges between calibration pulses. (Message length
is pre-defined by each sensor device and programmed by user for each channel)
•
Checksum error. Two 4-bit CRC checks and one 6-bit CRC check according to the
message type. User has a programmable option to select the method of CRC to use
i.e. Legacy or XOR-based.
•
Any nibble data values measured as < 0 or > 15
•
Successive calibration pulses differ by > +1.5625% (1/64) or < -1.5625%. The accuracy
of this check will depend on the frequency of the protocol clock used.
•
For messages with pause pulse, an additional diagnostic is done; however, this
diagnostic will not fail any message (to reduce latency in message reception) but the
failure of this diagnostic will be indicated in the channel's status register.
On detection of any of the above errors, the receiver rejects the current packet until a new
calibration pulse is detected. Occurrence of an error is flagged in the respective channel's
status register
(CHn_STATUS)). If error interrupt is enabled, an error interrupt will be generated. There is a
single error interrupt generated for all errors, so the CPU must read the status register to
find out which error occurred. Once error condition is flagged, subsequent errors (except
NUM_EDGES_ERR) are automatically masked out until a valid calibration pulse is
(Section 49.3.2.20: Channel 'n' Configuration Register (n = 0 to (CH-
(Section 49.3.2.20: Channel 'n' Configuration Register (n = 0 to (CH-
Figure 803. Input programmable filter timing diagram
0 1 2 3 4 5 6 7 0 1 2 3 4 5 0 1 2
(Section 49.3.2.19: Channel 'n' Status Register (n = 0 to (CH-1))
DocID027809 Rev 4
SENT Receiver (SRX)
Figure 803.
0 1 2 3 4 5 6 7 8
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