Overview - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
63.1.2

Overview

The SPU is able to generate complex debug events, based upon input events from sources
(CPUs, GTM, and system bus clients) throughout the SoC. The SPU has the ability to
create a state machine to trigger a debug action. Single or multiple actions can be triggered
by a state machine, which results in debug events being created. There are a selection of
timers and counters available to assist comparison events.
Complex trigger support is implemented in the State Logic Unit (SLU). There are numerous
inputs coming from different clients. Users can choose 63 inputs from a set of 209 inputs at
the level one Mux. There are actually 64 inputs to the Muxes, but one of the inputs is
permanently connected to a high level so users can only choose 63 of the inputs. Of these
63 inputs, users can select 16 inputs for each SLU, shown in
One SLU consists of four input AND gates, the output of which are ORed together. One of
the inputs of each AND gate has the option to invert it. Also, the output of each AND gate
can be optionally inverted. Finally, the output of each SLU has the option of inversion. The
block diagram for one SLU state is shown in
states.
Users can utilize these states to form a configurable state machine. This allows users to join
states together with the if-then-else operations to create a sequence. Each state in a
sequence has the ability to move to another state based on the true condition from the state
logic, and the ability to route to another state based on the a false condition from the state
logic. This is shown in
sequences are allowed. Each sequence can have one state or maximum of eight states.
Each state can only be used in one unique sequence. The number of states in all the
sequences cannot exceed eight. Each state has the ability to trigger one to four actions
based on a true/false condition in the active sequence.
An example of typical complex trigger for the SPU would be: if FunctionA is entered,
monitor CPU0 writes to VariableB. If CPU0 writes a value to VariableB which is 0x100, then
enable trace for the GTM and halt CPU0.
The SPU consists of the following sub-blocks:
•
Input Mux Unit—receives the numerous triggers from various clients and reduces them
down into a user selected set. The muxing unit selects sixteen inputs for each
sequencing SLU from a set of 63 static inputs. This selection is done using two levels of
muxing. At the first level of muxing, users select 63 out of 209 inputs. At the second
level of muxing, out of these 63 inputs, one input can be selected for each of the four
input AND gates. There are 128 64 × 1 Muxes to cater the needs of 128 inputs of all the
eight states. This input mux selection logic is shown in
• State Logic Units (SLU)—responsible for performing operations on the selected input
events to produce desired events. Each SLU has a control register that manages how
the various inputs are combined to produce a desired event. Only one input of each
four input AND gate can be independently inverted. The combined event can also be
optionally inverted and, coupled with DeMorgan's law, allows for generalized signal
combinations. This is shown in
•
Action Processing Unit—takes an action request from a SLU state and converts this
into one or multiple actions. The action unit can be programmed to trigger various
actions in response to each processed event from the SLU unit. The user can define
the actions associated with each state from each SLU.
•
Counters/Timers—The SPU implements 16 32-bit timer/counter functionality. Timer or
counter selection is done via a configurable register in the SPU. Each counter/timer
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Figure 1099 and Figure
Figure 1098.
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Figure
Figure 1098. The SPU includes eight SLUs
1100. At a given time, a maximum of four
Figure
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1097.