Memory Map And Register Definition - STMicroelectronics SPC572L series Reference Manual

GTM101 Integration (GTMINT) Module
From/To
CPU
Clocks
I/O
signals
Clocks
43.2

Memory map and register definition

This section provides a reference table to the GTM-IP submodule registers. Details of each
register are found in the GTM-IP specification document. Additional registers from those
used in the GTM-IP are described in this section.
43.2.1 Module memory map
The GTMINT simplified memory map is shown in
GTMINT base address. See the device memory map for the module base address.
Note: The GTMINT module has only a few registers, detailed in
descriptions. The module also acts as an interface to all implemented GTM-101 control
registers. For details see the GTM-IP Specification document.
Offset
0x00000000
0x000000C0
0x00000100
0x00000180
0x00000200
0x00000280
964/2058
Figure 466. GTMINT block diagram
CPU
Interface
Table 515. High level memory map
DocID027809 Rev 4
GTM-IP
GTMDI
Debug
Interface
Table 515. Offsets are relative to the
Section 43.2.2, Register
(1)
Use
GTM-IP TOP-Level Configuration Registers
GTM-IP Integration Registers
TBU
MON
CMP
ARU
To/From
IRQ/
INTC &
DMA
DMAC
To/From
RAMs
ECC
To
MEMU
RM0400