Linflexd - Configurations; Linflexd Implemented Registers - STMicroelectronics SPC572L series Reference Manual

RM0400
Offset
0x0194 CH2_FMSG_CRC—Channel 'n' Fast Message CRC Register
0x0198 CH2_FMSG_TS—Channel 'n' Fast Message Time Stamp Register
0x019C CH2_SMSG_BIT3—Channel 'n' Serial Message Register (Bit 3)
0x01A0 CH2_SMSG_BIT2—Channel 'n' Serial Message Register (Bit 2)
0x01A4 CH2_SMSG_TS—Channel 'n' Serial Message Time Stamp Register
0x01A8 CH3_FMSG_DATA—Channel 'n' Fast Message Register
0x01AC CH3_FMSG_CRC—Channel 'n' Fast Message CRC Register
0x01B0 CH3_FMSG_TS—Channel 'n' Fast Message Time Stamp Register
0x01B4 CH3_SMSG_BIT3—Channel 'n' Serial Message Register (Bit 3)
0x01B8 CH3_SMSG_BIT2—Channel 'n' Serial Message Register (Bit 2)
0x01BC CH3_SMSG_TS—Channel 'n' Serial Message Time Stamp Register
0x01C0 – 0x02E0 Reserved
6.7.6 LINFlexD – Configurations
SPC572Lx has three instances of LINFlexD.
instance.
Description
Number of filters implemented
Number of Tx DMA channels
Number of Rx DMA channels
LIN operation mode
Value of autosynchronization
6.7.7

LINFlexD implemented registers

Table 50
chip.
Register description
LIN Control register 1 (LINCR1)
LIN Interrupt Enable register (LINIER)
LIN Status register (LINSR)
Table 48. SENT receiver memory map(Continued)
Table 49. LINFlexD configurations
shows the registers implemented for each LINFlexD instance on the SPC572Lx
Table 50. LINFlexD implemented registers
DocID027809 Rev 4
Register name
Table 49 lists the configuration for each
linflex_0
16
1
1
Master/Slave
1
linflex_0
0xFFE8C000
Address offset Address offset
(hex)
00
04
08
Device configuration
linflex_1 linflex_14
0
1
1
Master
0
linflex_1 linflex_14
0xFFE90000 0xFFEA8000
Address offset
(hex)
00
04
08
SENT 0
X
X
X
X
X
X
X
X
X
X
X
—
0
1
1
Master
0
(hex)
00
04
08
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