Error Handling - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Nexus 3 Module
Otherwise, if the access has completed with an error, the nex_err_b pin will be
asserted, the ERR bit will be set and the DV bit will be cleared to indicate an error has
occurred, the AC bit is cleared and the block transfer is aborted, and the nex_rdy_b
pin will not be asserted. Once ERR or DV has been set, this indicates that the device is
ready for the next access, or that an error has occurred. Once DV has been set, this
indicates that the device is ready for the next access in the block transfer, or if ERR is
set (AC will be cleared), the block transfer has been aborted.
4. The data can then be read from the Read/Write Access Data Register (RWD) through
the access method outlined in
5. If AC has not been cleared due to an error, repeat Steps 3 and 4 in
Single read access
the RWCS is cleared to indicate the end of the block read access.
Note: The data values must be shifted out 32 bits at a time LSB first (i.e. doubleword read = two
word reads from the RWD).
Note: The actual RWA value as well as the CNT field within the RWCS are not changed when
executing a block read access. The original values can be read by the external development
tool at any time.
66.17.5

Error handling

The Nexus 3 module handles various error conditions as follows:
66.17.5.1 AHB Read/Write error
All address and data errors that occur on read/write accesses to the AHB system bus will
return a transfer error encoding on the p_hresp[1:0] signals. If this occurs:
1. The access is terminated without retrying (AC bit is cleared).
2. The ERR bit in the RWCS Register is set.
3. The Error Message is sent (TCODE = 8) indicating Read/Write error.
66.17.5.2 Access termination
The following cases are defined for sequences of the Read/Write protocol that differ from
those described in the above sections.
1. If the AC bit in the RWCS Register is set to start Read/Write accesses and invalid
values are loaded into the RWD and/or RWA, then an AHB access error may occur.
This is handled as described above.
2. If a block access is in progress (all cycles not completed), and the RWCS Register is
written, then the original block access is terminated at the boundary of the nearest
completed access.
a)
b)
66.17.6 Read/Write access error message
The Read/Write Access Error Message is sent out when an AHB system bus access error
(read or write) has occurred.
1972/2058
until the CNT value is zero (0). When this occurs, the AC bit within
If the RWCS is written with the AC bit set, the next Read/Write access will begin
and the RWD can be written to/ read from.
If the RWCS is written with the AC bit cleared, the Read/Write access is
terminated at the nearest completed access. This method can be used to break
(early terminate) block accesses.
DocID027809 Rev 4
Section 66.5, Nexus 3 Register Access via
RM0400
JTAG/OnCE.
Section 66.17.3,