Dspi Status Register Extended (Dspi_Srex) - STMicroelectronics SPC572L series Reference Manual

RM0400
46.3.28 DSPI Clock and Transfer Attributes Register Extended (DSPI_CTAREn)
CTARE registers are used to define the extended transfer attributes for an SPI frame.
These registers are valid only when DSPI_MCR[XSPI] is set.
When the DSPI is configured as:
•
an SPI master, the CTAS field in CMD FIFO entry selects which of the CTARE registers
is used.
•
an SPI bus slave, the CTARE0 register is used.
Address: Base + 0x011C
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Figure 611. DSPI Clock and Transfer Attributes Register Extended (DSPI_CTAREn)
Field
Frame Size Extended
This field concatenated with DSPI_CTAR[FMSZ] defines the frame size of the SPI frames to be
transmitted.
16
Frame size is the concatenation of {DSPI_CTAR[FMSZ], DSPI_CTARE[FMSZE]} + 1.
FMSZE
0Default Mode. Up to 16-bit SPI frames can be transferred.
1Up to 32-bit SPI frames can be transferred. Each frame transfer is a result of 2 TX FIFO Pops.
Data Transfer Count Preload
This field defines the number of data frames (whose size is defined by CTARE[FMSZE] and
21–31
CTAR[FMSZ]) to be transmitted using the Command frame that selected this DSPI_CTARE
DTCP
register.
The value 0 is reserved and should not be written in this field. The default value of this field is 1.
46.3.29

DSPI Status Register Extended (DSPI_SREX)

The DSPI_SREX contains status fields that reflect the DSPI status and indicate the
occurrence of events.
This register is not writable.
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0
0 0 0 0
Table 640. DSPI_CTAREn field descriptions
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
DTCP
0 0 0 0
14 15
0
0 0
30 31
0 1
1177/2058
1220