Dspi Dsi Serialization Data Register 0 (Dspi_Sdr0) - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
Field
DSI Clock and Transfer Attributes Select (DSI Master mode only)
17–19
Selects the CTAR which provides transfer attributes for DSI frames.
DSICTAS[2:0]
In DSI slave mode, CTAR1 is always selected.
Data Match Stop
20
Stops DSI frame transmissions if DDIF flag is set in the status register.
DMS 0 Disabled.
1 Enabled.
Parity Error Stop
21
Stops DSI operation if a parity error occurred in the received DSI frame.
PES 0 Disabled.
1 Enabled.
Parity Enable
Enables parity bit transmission and parity reception check for the DSI frames.
22
0 No parity bit included/checked.
PE
1 Parity bit is transmitted instead of the last data bit in the frame; parity is checked for the received
frame.
Parity Polarity
Controls the polarity of the parity bit transmitted and checked.
23
0 Even Parity: the number of '1' bits in the transmitted frame is even. The SR[DPEF] bit is set if
PP in the received frame number of '1' bits is odd.
1 Odd Parity: the number of 1 bits in the transmitted frame is odd. The SR[DPEF] bit is set if in
the received frame number of 1 bits is even.
DSI Peripheral Chip Select 0–7
24–31
Selects which of the PCS signals to assert during a DSI master mode transfer.
DPCSx 0 Negate PCS[x].
1 Assert PCS[x].
46.3.13

DSPI DSI Serialization Data Register 0 (DSPI_SDR0)

Read-only SDR0 contains the states of the 32 LSB parallel input signals.
The states of these signals are latched into the SDR0 on the rising edge of every protocol
clock.
When the TXSS bit in the DSICR0 is cleared, the data in the SDR0 is used as the source of
the DSI frames.
When DSICR1[DSI64E] is set, SDR1 is the MSB half and SDR0 is the LSB half of the 64-bit
SDR.
1166/2058
Table 624. DSPI_DSICR0 field descriptions(Continued)
DocID027809 Rev 4
Description
RM0400