Calibration and Debug
Field
000 Reserved
001 Reserved
010 Reserved
011 Reserved
MUX43
100 Reserved
101 Reserved
110 SPU counter event 3
111 GTM watchpoint 11
000 Reserved
001 Reserved
010 Reserved
011 Reserved
MUX 44
100 Reserved
101 Reserved
110 SPU counter event 4
111 Reserved
000 Reserved
001 Reserved
010 Reserved
011 Reserved
MUX 45
100 Reserved
101 Reserved
110 SPU counter event 5
111 Reserved
000 CPU return (watchpoint 17)
001 CPU critical return (watchpoint 19)
010 CPU data trace control range 2 (watchpoint 30)
011 Reserved
MUX 46
100 Reserved
101 Reserved
110 SPU counter event 6
111 Reserved
000 Reserved
001 Reserved
010 Reserved
011 Reserved
MUX 47
100 Reserved
101 Reserved
110 SPU counter event 7
111 Reserved
Table 86
250/2058
Table 85. L1SEL5 register field descriptions(Continued)
contains the L1SEL6 register field descriptions.
DocID027809 Rev 4
Description
RM0400
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