Line Receiver (Lr) - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
47.7.1.2 LFAST slave interface startup procedure
1. After reset the SLCR and RCDCR are programed according to the LVDS parameters in
the device datasheet.
2. The LCR is programed with the configuration parameters for the LVDS.
3. Write MCR[MSEN] = 0. Then select LFAST modes by configuring MCR[CTSEN] and
MCR[DATAEN].
4. Write MCR[DRFEN] = 1 to enable the LFAST.
5. The LR is enabled by writing MCR[RXEN] = 1. This negates the LR disable signal and
LR's power down signal.
6. The LD enable signal needs to be asserted. This is done when one of the following are
true:
–
–
7. After a write to MCR[TXARBD] = 0, a ping frame will be sent on one of the following
conditions:
–
–
Speed mode change:
8. The speed of the Tx interface is changed on one of the following conditions:
–
–
9. The speed of the Rx interface is changed on one of the following conditions:
–
–
10. A Ping Frame is sent on one of the following conditions:
–
–
47.7.2

Line Receiver (LR)

47.7.2.1 Introduction
The LR detects the voltage swing on the differential pair and converts it to a CMOS logic
level that feeds the adaptive auto-correlation block. The received data is sampled using the
best of the 8 (default) or 4 (alternative setting) possible sampling edges from the high speed
clock or 4 phases using the low speed clock. The sampling edge is chosen by checking
which of the 8/4 Correlators provide the maximum correlation. If more than one sampling
edge provides the maximum then the state machine will choose the sampling edge based
on a defined selection algorithm.
After the correct sampling edge is chosen, the remaining unused sampling edges are turned
off. Once the header is received the length of the frame (payload size) and logical channel
When an ICLC frame with payload 31h is received the H/W will write
RIISR[ICTEF] = 1 and MCR[TXEN] = 1.
MCRMCR[TXEN] = 1
When PICR[PNGAUTO] = 1 and an ICLC frame with payload 00h frame is
received.H/W writes [ICRPF] = 1
PICR[PNGREQ] = 1.
When SCR[DRMD] = 1 and an ICLC frame with payload 80h is received. H/W
writes RIISR[ICTFF] = 1 and SCR[TDR] = 1.
SCR[TDR] = 1 when SCR[DRMD] = 0
When SCR[DRMD] = 1 and an ICLC frame with payload 10h is received. H/W
writes RIISR[ICRFF] = 1 and SCR[RDR] = 1.
SCR[RDR] = 1, when SCR[DRMD] = 0
When PICR[PNGAUTO] = 1 and an ICLC frame with payload 00h is received.H/W
writes RIISR[ICRPF] = 1
Write PICR[PNGREQ] = 1.
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