Table 900. Ie_P Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Power Management Controller digital interface (PMC_dig)
Field
VD3_C low-voltage detect flag—low voltage Core cold point 1.08 V supply.
28
0 No occurrence has happened, or EPR_VD3[LVD3_C] has been cleared.
VD3_C
1 LVD occurrence detected.
29–30 Reserved.
VD2_C low-voltage detect flag—low voltage 0.98 V Core hot point supply.
31
0 No occurrence has happened, or EPR_VD2[LVD2_C] has been cleared.
VD2_C
1 LVD occurrence detected.
54.3.1.3 Interrupt Enable Pending register (IE_P)
This configuration register contains a set of Interrupt Enable bits that correspond to each of
the Event Pending registers in a similar format to the Pending Gauge Status register
(GR_P). These bits toggle whether an interrupt occurs when the voltage event is seen:
Writing '1' to the MSB (IE_P[IE_EN]) enables all of the voltage detect bits in the register to
be read or written at any time.
Offset: PMC_BASE + 0x0008
0 1
R 0
W
Reset 0 0
16 17
R
W
Reset 0 0
Field
IE_EN. Interrupt Enable.
0
0 No interrupt enables can be written.
IE_EN
1 Any interrupt enable can be written.
1–8 Reserved.
VD14IE_A Interrupt Enable.
9
0 No interrupt occurs.
VD14IE_A
1 An interrupt occurs on a voltage detect event.
VD14IE_IM Interrupt Enable.
10
0 No interrupt occurs.
VD14IE_IM
1 An interrupt occurs on a voltage detect event.
1576/2058
Table 899. GR_P field descriptions(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0
0 0 0 0
Figure 938. Interrupt Enable Pending register (IE_P)

Table 900. IE_P field descriptions

DocID027809 Rev 4
Description
6 7 8 9
0 0 0
0 0 0 0
22 23 24 25
0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0
0 0 0 0
26 27 28 29
0 0 0
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
0
0 0