Functional Description; General; Pad Control - STMicroelectronics SPC572L series Reference Manual

System Integration Unit Lite2 (SIUL2)
Field
Mask Field—Each bit corresponds to one data bit in the MPPDO[x] register at the same bit
0–15
location.
MASK[x]
0 The associated bit value in the MPPDO[x] field is ignored
[0:15]
1 The associated bit value in the MPPDO[x] field is written
Masked Parallel Pad Data Out—Write the data register that stores the value to be driven on the
16–31
pad in output mode. Access to this register location are coherent with access to the bit-wise
GPIO Pad Data Output Registers (PDO). The x and bit index define which MPPDO register bit is
MPPDO[x]
equivalent to which PDO register bit according to the following equation:
[0:15]
MPPDO[x][y] = PDO[(x*16)+y]
13.3

Functional description

13.3.1

General

This section provides a complete functional description of the SIUL2.
13.3.2

Pad control

The SIUL2 is capable of controlling the electrical characteristic of 85 pads on this device. It
provides a consistent interface for all pads, both on a by-port and a by-bit basis. The
following describes the pad characteristics that can be supported by the SIUL2. Not all of
these features will be supported on all devices or on all pads as this is dependent on the
specific application needs and the pads implemented on the device.
The required controls are:
•
Drive strength control
–
–
• Internal weak pull capability
–
–
•
Control of analog path switches
•
Safe Mode behavior configuration
•
Open drain/source enable
–
•
Pin Function Assignment
–
The setting of each pad out of reset is fixed per MCU, but can be configured individually. In
this way it is possible to select special pull settings or peripheral pad ownership per design.
It is possible for the user software to configure each pad independently of all other pads on
the device or other pads grouped within a single port. This allows different pad types to be
grouped together in ports and allows the necessary flexibility needed for the pads individual
304/2058
Table 131. SIUL2_MPGPDO0 field description
This is needed to offer improved EMC performance.
Up to 4 different drive strength levels can be supported.
This is needed to offer flexibility in the device configuration and the elimination of
external hardware in some cases.
The configuration of the pull on any pad should be independently controlled to be
either pull-up, pull-down or no-pull enabled.
Needed to support different pads muxed (e.g., mux IIC, with non open drain pads)
This setting defines which chip function has control over the output of the pad.
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Description
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