Hardware Request Status Register Low (Dma_Hrsl) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Error in channel 5
26
0 An error in the corresponding channel has not occurred
ERR5
1 An error in the corresponding channel has occurred
Error in channel 4
27
0 An error in the corresponding channel has not occurred
ERR4
1 An error in the corresponding channel has occurred
Error in channel 3
28
0 An error in the corresponding channel has not occurred
ERR3
1 An error in the corresponding channel has occurred
Error in channel 2
29
0 An error in the corresponding channel has not occurred
ERR2
1 An error in the corresponding channel has occurred
Error in channel 1
30
0 An error in the corresponding channel has not occurred
ERR1
1 An error in the corresponding channel has occurred
Error in channel 0
31
0 An error in the corresponding channel has not occurred
ERR0
1 An error in the corresponding channel has occurred
Note: These bits reflect the state of the request as seen by the arbitration logic. Therefore, this
status is affected by the ERQ{H,L} bits.
19.3.15

Hardware Request Status Register Low (DMA_HRSL)

The HRSL provides a bit map for the DMA channels, signaling the presence of a qualified
hardware service request for each channel. HRSL covers channels 15–00. The Hardware
Request Status bits reflect the current state of the register and qualified (via the ERQL
fields) DMA request signals as seen by the DMA's arbitration logic. This view into the
hardware request signals may be used for debug purposes.
Note: These bits reflect the state of the request as seen by the arbitration logic. Therefore, this
status is affected by the ERQL bits.
Address: FC0A_0000 + 0x0034
0 1
R 0 0
W
Reset 0 0
16 17
R HRS
HRS
15 14
W
Reset 0 0
Figure 133. Hardware Request Status Register Low (DMA_HRSL)
Table 178. DMA_ERRL field descriptions(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
HRS HRS HRS HRS
13 12 11 10
0 0 0 0
DocID027809 Rev 4
Enhanced Direct Memory Access (eDMA)
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
HRS HRS HRS HRS
9 8 7 6
0 0 0 0
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
HRS HRS HRS HRS
5 4 3 2
0 0 0 0
14 15
0 0
0 0
30 31
HRS HRS
1 0
0 0
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