Tion - STMicroelectronics SPC572L series Reference Manual

Clock Generation Module (MC_CGM)
In this case, system clock divider 1 has a division factor greater than that of system clock divider 0. Since
2 is an integer multiple of 1, its configration is correct. Also, system clock divider 3 has a division factor
that is greater than those of both system clock dividers 0 and 1. Since 6 is an integer multiple of 1 and 6
is an integer multiple of 2, its configuration is also correct.
Table 272. MC_CGM Example System Clock Dividision Values Incompatible with Divider
Divider
0
1
2
In this case, system clock divider 1 has a division factor greater than that of system clock divider 0. Since
4 is an integer multiple of 1, its configuration is correct. Also, system clock divider 3 has a division factor
that is greater than those of both system clock dividers 0 and 1. Since 6 is not an integer multiple of 4, its
configuration is incorrect.
Warning: Configuring the system clock dividers incorrectly will cause the divided
clocks to become unsynchronized. This may lead to lost communication
between the clock domains and/or the inability to further change the
system clock divider division factors without first disabling them or
performing a reset.
24.4.1.4.2 System Clock Divider Update Triggering
As opposed to the auxiliary clock dividers which update immediately on a configuration change, the
system clock dividers are updated only with the next software triggered mode change. This is to ensure
that the system clock dividers are updated simultaneously and that no intermediate inconsistent
configurations can occur. It also ensures that the divider configurations are aligned with the target mode's
system clock selection.
The system clock divider configuration update sequence is as follows:
1. Configure the target mode in the MC_ME to select the desired system clock source.
2. Configure the CGM_SC_DC0...2 registers as desired and aligned with the target system clock
source frequency making sure that the dividers are configured consistently as described in
Section 24.4.1.4.1, System Clock Divider
3. Request a mode change in the MC_ME to the desired target mode.
4. When mode change has completed and the system clock switching has been successfull, the new
system clock divider configuration will be in effect.
See the MC_ME chapter for details on how to configure modes and make mode change requests.
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Example 2. Incorrect System Clock Divider Configuration
Division Factor
1
4
6
Synchronization
CGM_SC_DC0[DIV] = 0
CGM_SC_DC1[DIV] = 3
CGM_SC_DC2[DIV] = 5
Synchronization.
DocID027809 Rev 4
Register Value
RM0400