Introduction - STMicroelectronics SPC572L series Reference Manual

Decimation Filter
37 Decimation Filter
37.1

Introduction

This chapter describes the Decimation Filter block.
37.1.1 Overview
The decimation filter is a dedicated hardware block, designed to decimate fixed point
sample conversion results. An interface is provided for use by the CPU, allowing setup of
the filter parameters and read/write of the configuration registers and filter samples.
The Decimation Filter receives data samples from the master blocks (CPU) in the RX sub-
block. Each sample arrives at the decimation filter with an identifier tag and associated
commands. The input information is decoded by the RX and control logic sub-blocks. When
receiving a filtering command, the data is transferred to the filter tap register's sub-block and
is processed by the filter using the MAC (Multiply and Accumulate) unit, the coefficient
register, and the control logic sub-blocks. The result is then returned to the master block by
the TX sub-block, accompanied by the corresponding tag information that provides an
address for the data.
The decimation filter functions in a standalone mode. In this mode, the input data is supplied
and the output results are read by the chip core processor (CPU) using status and interrupt
signals or DMA requests.
An integrator unit independently accumulates the values of filter outputs. The integration
can be restricted to time windows defined by hardware signals or software.
All signals in the interface are generated in the system clock domain.
Figure 359
804/2058
shows the block diagram for the decimation filter.
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