Table 1034. Ints Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
0 1 Interrupt status bit is cleared from JTAGM
INT
31–1 Reserved
63.5.1.7 Counters control n (CCTRLn) registers
There are 16 configurable counters/timers in the SPU. Configuration control of these
counters is defined in the counter control registers.
CCTRLn registers where the counter number, n = 0–15.
Offset 0x26–0x35 (CCTRL0–15)
31 30 29 28 27 26 25
R 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0
15 14 13 12 11 10 9
R 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0
The CCTRLn register fields are described in
Field
Enable.
0
0 Counter disabled
ENABLE
1 Counter enabled
Mode Select. Select counter or timer operation.
1
0 Counter
MODE
1 Timer
Count Increment.
2
0 Increment the counter based on the actions generated from the sequences
COUNT_INCR
1 Increment the counter based on the PMC input.
3 Reserved. Read returns 0.

Table 1034. INTS register field descriptions

24 23
0 0
0 0
8 7
0
SW_RESET
0
0 0
Figure 1092. CCTRLn register format
Table 1035. CCTRLn register field descriptions
DocID027809 Rev 4
Sequence Processing Unit (SPU)
Description
Figure 1092
22 21 20 19
0 0 0 0
0 0 0 0
6 5 4 3
0
PRESCALING COUNT_INCR MODE
0 0 0 0
Table 1035.
Description
shows the format of the
Access: User read/write
18 17
0 0
0 0
2 1
ENABLE
0 0
1851/2058
16
0
0
0
0
1863