Table 118. Siul2_Dirsr0 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

System Integration Unit Lite2 (SIUL2)
Field
27 Reserved
28–31
EIRE3
External Interrupt or DMA Request Enable x
EIRE2
0 Interrupt or DMA requests from the corresponding EIF[x] bit are disabled
1 Set EIF[x] bit causes either a DMA or an interrupt request depending on SIUL2_DIRSR
EIRE1
EIRE0
13.2.2.5 SIUL2 DMA/Interrupt Request Select Register 0 (SIUL2_DIRSR0)
The DIRSR selects between the DMA or interrupt request. If the corresponding bits are set
in SIUL2 DMA/Interrupt Status Flag Register0 (SIUL2_DISR0) and SIUL2 DMA/Interrupt
Request Enable Register0 (SIUL2_DIRER0), then the DMA/Interrupt Request Select bit
determines whether DMA or an interrupt request is asserted. EIRQ are the external interrupt
package pins on the device.
Address: 0x0020
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Figure 58. SIUL2 DMA/Interrupt Request Select Register 0 (SIUL2_DIRSR0)
Field
0–20 Reserved
DMA/Interrupt Request Select Register—Selects between DMA request or external interrupt
21 request when an edge-triggered event occurs on the corresponding pin.
DIRS10 0 Interrupt request is selected
1 DMA request is selected
22–25 Reserved
DMA/Interrupt Request Select Register—Selects between DMA request or external interrupt
26 request when an edge-triggered event occurs on the corresponding pin.
DIRS5 0 Interrupt request is selected
1 DMA request is selected
292/2058
Table 117. SIUL2_DIRER0 field descriptions(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0
DIRS
10
0 0 0 0

Table 118. SIUL2_DIRSR0 field descriptions

DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0
DIRS DIRS DIRS
5 3 2
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
DIRS DIRS
1 0
0 0