Table 663. Icr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
Field
0-13 Reserved
ICLC enabled. This bit should be set whenever the S/W is performing a series of ICLC frame
transfers. This bit ensures only ICLC frame transmission request is serviced, other pending frames
14 request are ignored.
ICLCSEQ 1 S/W is performing ICLC frame transfers. Only the ICLC frames will be scheduled during this period.
All the other frames will be scheduled only after ICR[ICLCSEQ] = 0.
0 Single ICLC frame transfer
ICLC frame request. This bit is set to initiate the transfer of ICLC frame by LFAST master. This bit
should be set (ICR[SNDICLC] = 1) after writing the required ICLC payload to be transmitted in the
15 ICLCPLD field of the register. This bit is self clearing, which will be cleared when ICLC frame transfer
is complete.
SNDICLC
1 Valid ICLC frame for transfer.
0 No Valid ICLC frame for transfer.
16-23 Reserved
ICLC Payload. This field is used to program the payload of the ICLC frame to be transmitted. New
24-31
ICLC payload should be set when ICR[SNDICLC] = 0.
ICLCPLD
Refer to
47.6.2.9 Ping Control Register (PICR)
Offset:
0020h
0 1
R 0 0
W
Reset 0 0
16 17
R 0
W
Reset 1 0
1
Only writable when MCR[DRFEN] = 0.
2
Set by user software and cleared by system hardware.

Table 663. ICR field descriptions

Table 687 for supported ICLC payloads.
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 649. Ping Control Register (PICR)
Description
6 7 8
0 0 0
0 0 0
22 23 24
0 0
0 0 1
DocID027809 Rev 4
Access: User read/write
9 10 11 12
0 0 0 0
0 0 0 0
25 26 27 28
1
PNGPYLD
1 0 0 1
13 14 15
0 0
0 0 0
29 30 31
0 1 0
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