STMicroelectronics SPC572L series Reference Manual page 738

Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface
Field
8 Reserved
Programmable Gain
This field selects the gain to be applied to the analog input stage of the SDADC. The effective
analog input becomes the input voltage level multiplied by the gain factor.
000 Gain = 1
001 Gain = 2
9–11
010 Gain = 4
PGAN
011 Gain = 8
100 Reserved
101 Reserved
110 Reserved
111 Gain = 16
12 Reserved
13 Reserved
External Modulator Selection
14
0 External modulator data and clock inputs are ignored
EMSEL
1 External modulator data stream and clock inputs are provided to SDADC
High Pass Filter Enable
15
0 High-pass (DC removal) filter is disabled
HPFEN
1 High-pass (DC removal) filter is enabled
16 Reserved
Trigger Edge Selection
17–18
00 Falling edge of trigger input is selected
TRIGEDSEL 01 Rising edge of trigger input is selected
1x Both edges of trigger input are selected
Trigger Enable
This field enables the hardware trigger input to initiate a fresh conversion. Upon receiving a
trigger event, SDADC reset input is asserted and deasserted synchronously with respect to
19
the peripheral clock. The reset pulse width is fixed to four peripheral clock cycles. The trigger
event is ignored if the SDADC internal modulator is not enabled (MCR[EN] = 0) or the
TRIGEN
external modulator is selected (MCR[EMSEL] = 1).
0 Trigger input is disabled
1 Trigger input is enabled
Trigger Input Selection
This field selects which input will be used for hardware-triggered conversions.
20–23
0000 Input trigger 0 is selected
TRIGSEL
0001 Input trigger 1 is selected
...
1111 Input trigger 15 is selected
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Table 358. MCR field descriptions(Continued)
DocID027809 Rev 4
Description
RM0400