Nexus Development Control Registers 2 & 3 (Dc2, Dc3) - STMicroelectronics SPC572L series Reference Manual

RM0400
Bits Name
7:6 —
5:0 TM
1. This field may be updated by hardware in response to watchpoint triggering or external hardware trigger inputs if not
already enable for tracing by a previous direct write to DC1. Direct writes to this field to enable one or more trace types take
precedence over hardware updates. Refer to
registers for more information on watchpoint triggering. Refer to
more information on external hardware triggering.
Note: The Output Port Mode Control bit (OPC) and MCKO Clock Divide Ratio bits (MCK_DIV)
MUST ONLY be modified during system reset or debug mode to insure correct output port
and output clock functionality. It is also recommended that all other bits of the DC1 also only
be modified in one of these two modes.
66.4.4 Nexus Development Control Registers 2 & 3 (DC2, DC3)
Nexus Development Control Registers 2 and 3 are used to control output signaling on the
Nexus 3 module. A table of watchpoints can be found in the Core (e200z215An3) Core
Debug Support chapter.
Development Control Register 2 is shown in
Table 1081.
WEVTO[3]C WEVTO[2]C WEVTO[1]C WEVTO[0]C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Table 1080. DC1 field descriptions(Continued)
Reserved for future functionality
(1)
Trace Mode
000000 — All Trace Disabled
xxxxx1 — Ownership Trace enabled
xxxx1x — Data Trace enabled
xxx1xx — Program Trace enabled
xx1xxx — Watchpoint Trace enabled
x1xxxx — Reserved
1xxxxx — Data Acquisition Trace enabled
Section 66.4.7, Watchpoint Trigger (WT, PTSTC, PTETC, DTSTC, DTETC)
Nexus Reg# 0x3; DCR: 369; Read/Write; Reset: 0x0
Figure 1133. Development Control 2 (DC2) register
DocID027809 Rev 4
e200z215An3 Nexus 3 Module
Description
Section 66.16, External Hardware Trigger Controls
Figure 1133 and its fields are described in
EWC
9
for
8 7 6 5 4 3 2
1923/2058
1 0
1982