Machine Check Syndrome Register (Mcsr) - STMicroelectronics SPC572L series Reference Manual

RM0400
12.6.3

Machine Check Syndrome Register (MCSR)

When the processor takes a machine check interrupt, it updates the Machine Check
Syndrome Register (MCSR) to differentiate between machine check conditions. The MCSR
is shown in
0
0 1 2 3 4 5 6
Table 97
condition.
All bits in the MCSR are implemented as "write 1 to clear." Software in the machine check
handler is expected to clear the MCSR bits it has sampled prior to re-enabling MSR
avoid a redundant machine check exception and to prepare for updated status bit
information on the next machine check interrupt.
Note that any set bit in the MCSR other than status-type bits will cause a subsequent
machine check interrupt once MSR
Table 97. Machine Check Syndrome Register (MCSR) field descriptions
Bit Name
0 MCP
(2)
1 IC_DPERR
2 —
(3)
3 DC_DPERR
4 EXCP_ERR
2
5 IC_TPERR
3
6 DC_TPERR
2
7 IC_LKERR
Figure 51.
0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR 572; Read/Clear; Reset: 0x0
Figure 51. Machine Check Syndrome Register (MCSR)
describes MCSR fields. The MCSR indicates the source of a machine check
Machine check input pin
Instruction Cache data array parity error
Reserved
Data Cache data array parity error
ISI or Bus Error on first instruction fetch for an exception
handler
Instruction Cache Tag parity error
Data Cache Tag parity error
Instruction Cache Lock error
Indicates a cache control operation or invalidation
operation invalidated one or more lines in a locked way of
the I-Cache for certain situations. May also be set on
locked line refill error.
DocID027809 Rev 4
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Description
Core e200z215An3 description
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Mchk
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Async
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